The present invention relates to a delay locked loop (DLL) circuit, and more particularly, to a DLL circuit for reducing power consumption in updating a delay value of an external clock after locking.
A synchronous semiconductor device such as a Double Data Rate Synchronous DRAM (DDR SDRAM) receives an external clock from an external device such as a memory controller and uses it as an internal clock of a semiconductor device. The synchronous semiconductor device transmits data to external devices using an inputted internal clock. Therefore, temporal synchronization between the external clock and data is very important in order to stably transmit data between a memory and a memory controller.
The external clock is inputted to the semiconductor device and distributed throughout the entire semiconductor device as an internal clock. The internal clock may be significantly delayed when the internal clock is transferred to a part that is comparatively far away from an input pin compared to an internal clock transferred to a part adjacent to the input pin. Therefore, a phase difference is generated between the internal clock and the external clock.
In order to overcome such a problem, the synchronous semiconductor device includes a clock synchronization circuit such as a delay locked loop (DLL) circuit. The DLL circuit generates an internal clock by compensating a clock delay component which is generated while transferring the internal clock to the data output end of the semiconductor device, thereby synchronizing the internal clock used for inputting and outputting final data of the semiconductor device with the external clock.
FIG. 1 is a block diagram illustrating a delay locked loop (DLL) circuit according to the related art.
As shown, the DLL circuit according to the related art includes a phase comparator 103, a replica unit 105, a delay controller 107, and a delay line unit 109.
The phase comparator 103 compares a phase of an external clock EXT_CLK with a phase of a feedback clock FB_CLK outputted from the replica unit 105. Here, the feedback clock FB_CLK is a clock modeled based on a clock delay component in the semiconductor device. The phase comparator 103 compares the phases by determining a logical level of the feedback clock FB_CLK at a rising edge of the external clock EXT_CLK and outputs a comparison signal CMP to the delay controller 107.
The delay controller 107 receives the comparison signal CMP and outputs a delay control signal DELAY for controlling a delay value Dd of the delay line unit 109 by deciding increment or decrement of the delay value Dd. The delay line unit 109 receives the delay control signal DELAY, delays the external clock EXT_CLK, and outputs the delayed external clock DL_CLK.
The delayed external clock DL_CLK is fed back to the replica unit 105. The delayed external clock DL_CLK is inputted to the phase comparator 103 through the replica unit 105 as a feedback clock FB_CLK. Then, the phase comparator 103 compares phases again and the above described processes are repeated until the phase of the external clock EXT_CLK is matched with the phase of the feedback clock FB_CLK.
If the phases of the external clock and the feedback clock FB_CLK are matched, the delay value Dd of the external clock EXT_CLK is locked in the DLL circuit (locking).
As shown, the DLL circuit according to the related art may further include a mode generator 113. The mode generator 113 receives the comparison signal CMP of the phase comparator 103 and decides an increment amount of the delay value Dd of the external clock EXT_CLK which can be a large increment or small increment. For example, if the phase difference between the external clock EXT_CLK and the feedback clock FB_CLK is great, the mode generator 113 generates a mode signal MODE to greatly increase the delay value Dd so as to quickly lock the DLL circuit. That is, the mode signal MODE is a signal for deciding one of a first mode for greatly increasing the delay value and a second mode for not greatly increasing the delay value.
The mode generator 113 also determines whether the DLL circuit is locked or not. For example, the mode generator 113 determines that the DLL circuit is locked if the phase comparator 103 alternatively outputs a high level comparison signal CMP and a low level comparison signal CMP. That is, if a ban bang error is generated, the mode generator 113 determines that the DLL circuit is locked. Since it is difficult to precisely match phases when the delay value Dd is digitally controlled, the phase comparator 103 may generate the bang bang error. If the delay value of the external clock EXT_CLK is locked in the DLL circuit, the mode generator 113 enables a locking signal LOCK and outputs the enabled locking signal LOCK.
The locking processes are stably controlled by the pulse generator 115 at the DLL circuit. FIG. 2 is a diagram illustrating a pulse signal of the pulse generator 115.
Referring to FIG. 2, the pulse generator 115 generates a plurality of pulse signals that are synchronized with the external clock EXT_CLK and have a regular period. The pulse signal of the pulse generator 115 sequentially enables each part of the DLL circuit.
That is, the pulse signal of the pulse generator 115 sequentially enables the phase comparator 103, the mode generator 113, and the delay controller 107 according to the locking processes. The pulse signal of the pulse generator 115 may be referred to as an enable signal of each element of the DLL circuit. The phase comparator 103 operates in response to a phase comparison enable signal PD_EN. The mode generator 113 operates in response to a mode enable signal MODE_EN and the delay controller 107 also operates in response to a delay control signal DELAY EN.
Operation results of each element are sustained until the next operation is performed, and the operations results may be used for the next operation. For example, a latch may be included at an output unit of the phase comparator 103 in order to sustain a phase comparison result between the enabling periods of the phase comparison enable signal PD_EN and the mode enable signal MODE_EN until an enable point of the mode enable signal MODE_EN where the mode generator 113 operates. According to design, various methods may be applied.
Referring to FIG. 1 again, if the delay value Dd is locked (locking) in the DLL circuit, an update process is performed. In the update process, a phase of the external clock EXT_CLK is compared with a phase of a feedback clock FB_CLK and the delay value Dd of the external clock EXT_CLK is corrected at a regular interval after locking. As described above, it is not necessary to frequently compare the phases of the external clock EXT_CLK and the feedback clock FB_CLK and to frequently control the delay value Dd of the external clock because the phases of the external clock EXT_CLK and the feedback clock FB_CLK are not greatly mismatched after locking. Therefore, enable signals having long intervals PD_EN, MODE_EN, and DELAY_EN are used in the update process compared with the enable signals in the locking process of the DLL circuit.
In the update process after locking, the delay value Dd of the external clock is corrected with a comparatively long interval compared to that for the locking process. That is, although the correction of the delay value Dd in the update process is performed less frequently than that in the locking process, the feedback clock FB_CLK is always toggled in the update process according to the related art. Therefore, the power consumption of the DLL circuit disadvantageously increases.